Layer 2 MAC (Medium Access Control) processing of radio communication digital baseband processing mainly consists of addition/deletion processing of a header part and encryption/decryption processing of a data part. A control processor in an apparatus realizes the MAC processing mainly by software processing while using a part of hardware for encryption/decryption processing. That is, the software processing of the control processor enables flexible coping so that contents of the MAC processing can vary in accordance with situations such as the number of data units in a data stream, bit strength of each data unit, encryption/decryption parameters and the like.
Here, processing of writing data before encryption/decryption processing and reading data after encryption/decryption processing is repeatedly performed for every encryption/decryption processing unit (for example, 64 bits) for the hardware for encryption/decryption processing. However, in future, there is a problem in which the processing load of the control processor is increased accompanied by an increase of bit rates of transmission/reception data in the radio communication and the processing fails when the above method is used to execute MAC processing.
Patent Document 1 (JP-A No. 2006-238214) discloses that a load is distributed to a plurality of sub-processors from a main processor with respect to decryption calculations of encryption data.
FIG. 1 is a view showing an operation that is performed when a main processor load-distributes to sub-processors authentication calculation or decryption calculation of an encryption key in a base station, which is disclosed in the Patent Document 1. The main processor instructs the sub-processors having small load on receiving a calculation request and the sub-processors perform the authentication calculation and the decryption calculation of an encryption key, so that the main processor is released from the processing of calculations.
However, when the above technology is applied to MAC processing, the encryption/decryption processing speed itself is not increased. Thus, the processing may not keep up with any future increase of bit rates. Further, it is not possible to mount the sub-processors on a portable terminal and the like when taking into consideration the area and power consumption.
Patent Document 2 (JP-A No. 11-505678) discloses that there is provided a dedicated integrated circuit module for encryption, so that codec processing and encryption processing of voice data are performed without data transmission by a control processor.
FIG. 2 is a view showing an example in which voice codec processing and encryption/decoding processing according to the prior art are combined into a single integrated circuit module, which is disclosed in the Patent Document 2. Since data transmission is not required between the voice codec processing and the encryption/decoding processing module in the integrated circuit, the overhead of the radio control processor is decreased.
However, if MAC processing is executed via a hardware-module by using the above technology, time to transmit the processing data to a MAC processing module from the control processor is required and it is not possible to input a plurality of data encryption/decryption processing at once (i.e., the control processor should be on standby). Further, if hardware is enabled to realize calculations of relatively complicated MAC processing parameters (encryption/decryption parameter, bit position or the number of bits of a header part or data part and the like), a high-speed and complicated hardware is required.
Patent Document 1 JP-A No. 2006-238214
Patent Document 2 JP-A No. 11-505678